This application claims the priority benefit of Taiwan application serial no. 90101008, filed Jan. 17, 2001.
1. Field of Invention
The present invention relates to a method of manufacturing a metal-oxide-semiconductor (MOS) device. More particularly, the present invention relates to a method of forming a dual damascene structure in a MOS device.
2. Description of Related Art
Multiple layer damascene techniques are frequently applied to form metallic interconnects having a line width smaller than 0.18 xcexcm. Metallic interconnects in different layers are often electrically connected by vias. Hence, the via-forming process is also important in the fabrication of metallic interconnects.
In a conventional interconnect fabrication process, a photoresist layer that serves as a mask must be formed. However, when the surface of the photoresist layer to the bottom of a via is more than 8000 xc3x85, light from a light source may not reach the photoresist material near the bottom of the via opening (depth exceeding 8000 xc3x85). Consequently, structural change to the positive photoresist may not occur and hence some photoresist may remain in the via after chemical development. The residual photoresist may react with low dielectric constant dielectric material in a subsequent step when the trench portion of a damascene opening is formed by etching. Ultimately, a short sidewall is formed in the area between the via and the trench close to the via sidewalls that may have some averse effects on the fabrication of interconnects.
Another conventional technique is to deposit a high molecular weight layer before coating the photoresist layer so that the effect of via depth on photoresist dissociation is minimized. This method is effective in preventing short sidewall. In general, however, different size openings and vias are form on a silicon wafer in MOS device fabrication. Thus, if a thin barrier layer is deposited over the wafer, high molecular weight layer of different thickness may form depending on the size of the vias and the openings. Subsequently, when the high molecular weight layer needs to be removed, the thinner high molecular weight layer at the bottom of large area openings may be over-etched leading to possible damages of bottom section of the opening. If the metallic layer at the bottom of the large area opening is damage, short-circuiting between interconnects may occur.
Accordingly, one object of the present invention is to provide a method of forming a barrier layer. The barrier material fills large area openings and vias of various sizes on a silicon wafer so that a flat wafer surface is obtained. The flat wafer surface prevents any residue photoresist material from sticking to the wafer surface after photo-exposure and photoresist development.
In addition, the barrier layer of this invention is flushed on the silicon wafer surface. In other words, the barrier plugs of various widths in different portions of the wafer all have an identical thickness. Hence, barrier plugs in various portions can be removed without causing any damages to the large area openings and vias of various sizes.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of forming a multiple layer damascene structure. A substrate comprising of a multi-layered stack that includes, from bottom to top, a metallic layer, a first etching stop layer, a first dielectric layer, a second etching stop layer and a second dielectric layer is provided. A photoresist layer having large area openings and vias pattern is formed over the substrate. Large area openings and vias that expose a portion of the first etching stop layer are formed in the substrate. A barrier layer that fills all the large area openings and vias is formed over the substrate. Chemical-mechanical polishing is conducted to remove a portion of the barrier layer and expose the second dielectric layer. A second photoresist having a trench pattern thereon is formed over the substrate. Using the second photoresist as a mask, etching is conducted so that the second etching stop layer around the vias is exposed. Lastly, the barrier layer is removed.
The barrier layer in this invention fills the large area openings and vias of various sizes so that a planar wafer surface is produced. Consequently, a photoresist layer having a uniform thickness can be formed in a multiple layer damascene process. Therefore, no residue photoresist material will remain in the light-exposed positions after photo-exposure and photoresist development.
The barrier plugs completely occupy the large area openings and the vias completely. Since uniformly thick barrier plugs are formed on the wafer surface independent of the size of the plug, damages to the bottom section of the large area openings and vias due to over-etching can be prevented.
In addition, the barrier layer is immediately formed after large area openings and vias are patterned out. Since there is no need to remove the photoresist layer first, a few production steps is saved compared with the conventional technique.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.